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SV51007
2014.01.10
LVDS Interface with External PLL Mode
6-9
LVDS Interface with External PLL Mode
The MegaWizard Plug-In Manager provides an option for implementing the LVDS interface with the Use
External PLL option. With this option enabled you can control the PLL settings, such as dynamically
reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings. You must also
instantiate the an Altera_PLL megafunction to generate the various clock and load enable signals.
If you enable the Use External PLL option with the ALTLVDS transmitter and receiver, the following signals
are required from the Altera_PLL megafunction:
?
?
?
?
Serial clock input to the SERDES of the ALTLVDS transmitter and receiver
Load enable to the SERDES of the ALTLVDS transmitter and receiver
Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
Asynchronous PLL reset port of the ALTLVDS receiver
Altera_PLL Signal Interface with ALTLVDS Megafunction
Table 6-7: Signal Interface Between Altera_PLL and ALTLVDS Megafunctions
This table lists the signal interface between the output ports of the Altera_PLL megafunction and the input ports of
the ALTLVDS transmitter and receiver. As an example, the table lists the serial clock output, load enable output,
and parallel clock output generated on ports outclk0, outclk1, and outclk2, along with the locked signal of the
Altera_PLL instance. You can choose any of the PLL output clock ports to generate the interface clocks.
From the Altera_PLL Megafunction
Serial clock output (outclk0)
The serial clock output (outclk0) can
only drive tx_inclock on the
ALTLVDS transmitter, and rx_
inclock and rx_dpaclock on the
ALTLVDS receiver. This clock cannot
drive the core logic.
Load enable output (outclk1)
Parallel clock output (outclk2)
To the ALTLVDS Transmitter
tx_inclock (serial clock
input to the transmitter)
tx_enable (load enable to
the transmitter)
Parallel clock used inside
To the ALTLVDS Receiver
rx_inclock (serial clock input)
rx_dpaclock
rx_enable (load enable for the
deserializer)
rx_syncclock (parallel clock input)
the transmitter core logic in and parallel clock used inside the
the FPGA fabric
receiver core logic in the FPGA fabric
~(locked)
—
pll_areset (asynchronous PLL reset
port)
The pll_areset signal is automatically
enabled for the LVDS receiver in
external PLL mode. This signal does
not exist for LVDS transmitter
instantiation when the external PLL
option is enabled.
Note: With soft SERDES, a different clocking requirement is needed.
High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
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